Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 251 of 1513
Aug 12, 2011
When the TAAnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts
each time the valid edge of external event count input is detected. Additionally, the set value of the TAAnCCR0 register is
transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, and a compare match interrupt request signal (INTTAAnCC0) is generated.
The INTTAAnCC0 signal is generated each time the valid edge of the external event count input has been detected (set
value of TAAnCCR0 register + 1) times.
Figure 7-16. Register Setting for Operation in External Event Count Mode (1/2)
(a) TAAn control register 0 (TAAnCTL0)
0/1 0 0 0 0
TAAnCTL0
0: Stops counting
1: Enables counting
000
TAAnCKS2 TAAnCKS1 TAAnCKS0 TAAnCE
(b) TAAn control register 1 (TAAnCTL1)
00000
TAAnCTL1
0, 0, 1:
External event count mode
001
TAAnMD2 TAAnMD1 TAAnMD0TAAnEEETAAnEST
(c) TAAn I/O control register 0 (TAAnIOC0)
00000
TAAnIOC0
0: Disables TOAAn0 pin output
0: Disables TOAAn1 pin output
000
TAAnOE1 TAAnOL0 TAAnOE0TAAnOL1
(d) TAAn I/O control register 2 (TAAnIOC2)
0 0 0 0 0/1
TAAnIOC2
Select valid edge of
external event count input
0/1 0 0
TAAnEES0 TAAnETS1 TAAnETS0TAAnEES1