Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 250 of 1513
Aug 12, 2011
7.5.2 External event count mode (TAAnMD2 to TAAnMD0 bits = 001)
In the external event count mode, the valid edge of the external event count input is counted when the
TAAnCTL0.TAAnCE bit is set to 1, and an interrupt request signal (INTTAAnCC0) is generated each time the specified
number of edges have been counted. The TOAAn0 pin cannot be used.
Usually, the TAAnCCR1 register is not used in the external event count mode.
Figure 7-14. Configuration in External Event Count Mode
16-bit counter
CCR0 buffer registerTAAnCE bit
TAAnCCR0 register
Edge
detector
Clear
Match signal
INTTAAnCC0 signal
TIAAn0 pin
(external event
count input)
Remark n = 0 to 3, 5
Figure 7-15. Basic Timing in External Event Count Mode
FFFFH
16-bit counter
0000H
TAAnCE bit
TAAnCCR0 register
INTTAAnCC0 signal
D 0
D 0 D 0 D 0
16-bit counter
TAAnCCR0 register
INTTAAnCC0 signal
External event
count input
(TIAAn0 pin input)
D 0
External
event
count
interval
(D
0 + 1)
D 0 − 1D 0 0000 0001
External
event
count
interval
(D
0 + 1)
External
event
count
interval
(D
0 + 1)
Remarks 1. This figure shows the basic timing when the rising edge is specified as the valid edge
of the external event count input.
2. n = 0 to 3, 5