Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 245 of 1513
Aug 12, 2011
(b) Operation if TAAnCCR0 register is set to FFFFH
If the TAAnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to
0000H in synchronization with the next count-up timing. The INTTAAnCC0 signal is generated and the output
of the TOAAm0 pin is inverted. At this time, an overflow interrupt request signal (INTTAAnOV) is not generated,
nor is the overflow flag (TAAmOPT0.TAAmOVF bit) set to 1.
FFFFH
16-bit counter
0000H
TAAnCE bit
TAAnCCR0 register
TOAAm0 pin output
INTTAAnCC0 signal
FFFFH
Interval time
10000H ×
count clock cycle
Interval time
10000H ×
count clock cycle
Interval time
10000H ×
count clock cycle
Remark m = 0 to 3, 5
n = 0 to 5