Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 242 of 1513
Aug 12, 2011
Figure 7-9. Register Settings for Interval Timer Mode Operation (2/2)
(c) TAAm I/O control register 0 (TAAmIOC0)
0 0 0 0 0/1
TAAmIOC0
0: Disables TOAAm0 pin output
1: Enables TOAAm0 pin output
Setting of output level with
operation of TOAAm0 pin disabled
0: Low level
1: High level
0: Disables TOAAm1 pin output
1: Enables TOAAm1 pin output
Setting of output level with
operation of TOAAm1 pin disabled
0: Low level
1: High level
0/1 0/1 0/1
TAAmOE1TAAmOL0 TAAmOE0TAAmOL1
(d) TAAn counter read buffer register (TAAnCNT)
By reading the TAAnCNT register, the count value of the 16-bit counter can be read.
(e) TAAn capture/compare register 0 (TAAnCCR0)
If the TAAnCCR0 register is set to D
0, the interval is as follows.
Interval = (D
0 + 1) × Count clock cycle
(f) TAAn capture/compare register 1 (TAAnCCR1)
Usually, the TAAnCCR1 register is not used in the interval timer mode. However, the set value of
the TAAnCCR1 register is transferred to the CCR1 buffer register. A compare match interrupt
request signal (INTTAAnCC1) is generated when the count value of the 16-bit counter matches
the value of the CCR1 buffer register.
Therefore, mask the interrupt request by using the corresponding interrupt mask flag
(TAAnCCMK1).
Remarks 1. TAAm I/O control register 1 (TAAmIOC1), TAAm I/O control register 2 (TAAmIOC2),
and TAAm option register 0 (TAAmOPT0) are not used in the interval timer mode.
2. m = 0 to 3, 5
n = 0 to 5