Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 241 of 1513
Aug 12, 2011
When the TAAnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
with the count clock, and the counter starts counting. At this time, the output of the TOAAn0 pin is inverted. Additionally,
the set value of the TAAnCCR0 register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, the output of the TOAAn0 pin is inverted, and a compare match interrupt request signal (INTTAAnCC0) is
generated.
The interval can be calculated by the following expression.
Interval = (Set value of TAAnCCR0 register + 1) × Count clock cycle
Remark m = 0 to 3, 5
n = 0 to 5
Figure 7-9. Register Settings for Interval Timer Mode Operation (1/2)
(a) TAAn control register 0 (TAAnCTL0)
0/1 0 0 0 0
TAAnCTL0
Select count clock
0: Stops counting
1: Enables counting
0/1 0/1 0/1
TAAnCKS2 TAAnCKS1 TAAnCKS0 TAAnCE
(b) TAAn control register 1 (TAAnCTL1)
0 0 0/1
Note
00
TAAnCTL1
0, 0, 0:
Interval timer mode
0: Operates on count clock
selected by TAAmCKS0
to TAAmCKS2 bits
1: Counts with external
event count input signal
000
TAAnMD2 TAAnMD1 TAAnMD0
TAAmEEETAmEST
Note This bit can be set to 1 only when the interrupt request signals (INTTAAmCC0 and INTTAAmCC1)
are masked by the interrupt mask flags (TAAmCCMK0 and TAAmCCMK1) and timer output
(TOAAm1) is performed. However, set the TAAmCCR0 and TAAmCCR1 registers to the same value
(see 7.5.1 (2) (d) Operation of TAAnCCR1 register).
Remark m = 0 to 3, 5
n = 0 to 5