Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 240 of 1513
Aug 12, 2011
7.5.1 Interval timer mode (TAAmMD2 to TAAmMD0 bits = 000)
In the interval timer mode, an interrupt request signal (INTTAAnCC0) is generated at any interval if the
TAAnCTL0.TAAnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOAAn0
pin.
Usually, the TAAnCCR1 register is not used in the interval timer mode.
Figure 7-7. Configuration of Interval Timer
16-bit counter
Output
controller
CCR0 buffer registerTAAnCE bit
TAAnCCR0 register
Count clock
selection
Clear
Match signal
TOAAm0 pin
INTTAAnCC0 signal
Remark m = 0 to 3, 5
n = 0 to 5
Figure 7-8. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
0000H
TAAnCE bit
TAAnCCR0 register
TOAAm0 pin output
INTTAAnCC0 signal
D 0
D 0 D 0 D 0 D 0
Interval (D 0 + 1) Interval (D 0 + 1) Interval (D 0 + 1) Interval (D 0 + 1)
Remark m = 0 to 3, 5
n = 0 to 5