Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 232 of 1513
Aug 12, 2011
(12) Noise elimination control register (TANFC)
Digital noise elimination can be selected for the TIAAn0 and TIAAn1 pins. The noise elimination setting is selected
using the TANFC register.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f
XX
and fXX/4. Sampling is performed 3 times.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution Time equal to the sampling clock × 3 clocks is required until the digital noise eliminator is
initialized after the sampling clock has been changed. If the valid edge of TIAAn0 and TIAAn1 is
input after the sampling clock has been changed and before the time of the sampling clock × 3
clocks passes, therefore, an interrupt request signal may be generated. Therefore, when using
the external trigger function, the external event function, and the capture trigger function of TAA,
enable TAA operation after the time of the sampling clock × 3 clocks has elapsed.
Remark n = 0 to 3, 5
TANFENTANFC 0 0 0 0 0 0 TANFC0
f XX
f XX /4
TANFC0
0
1
Digital sampling clock
After reset: 00H R/W Address: FFFFF724H
Does not perform digital noise elimination
Performs digital noise elimination
TANFEN
0
1
Setting of digital noise elimination
Remarks 1. Since sampling is performed 3 times, the noise width for reliably eliminating
noise is 2 sampling clocks.
2. In the case of noise with a width smaller than 2 sampling clocks, an
interrupt request signal is generated if noise synchronized with the
sampling clock is input.