Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 1 INTRODUCTION
R01UH0042EJ0500 Rev.5.00 Page 23 of 1513
Aug 12, 2011
Watchdog timer: 1 channel
{ Real-time output port: 6 bits × 1 channel
{ Serial interface: Asynchronous serial interface C (UARTC)
3-wire variable-length serial interface F (CSIF)
I
2
C bus interface (I
2
C)
CAN interface
USB function interface
UARTC/CSIF: 2 channels
UARTC/CSIF/I
2
C: 1 channel
UARTC/I
2
C
Note
: 2 channels
CSIF: 2 channels
USB function: 1 channel
Note In the
μ PD70F3770 and 70F3771, one channel is shared with CAN.
{ A/D converter: 10-bit resolution: 12 channels
{ D/A converter: 8-bit resolution: 2 channels
{ DMA controller: 4 channels
{ DCU (debug control unit): JTAG interface
{ Clock generator: Main clock or subclock operation:
7-level CPU clock (f
XX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
Clock-through mode/PLL mode selectable
{ Internal oscillation clock: 220 kHz (TYP.)
{ Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
{ Package: 100-pin plastic LQFP (fine pitch) (14 × 14) (V850ES/JG3-H)
128-pin plastic LQFP (fine pitch) (14 × 20) (V850ES/JH3-H)