Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 225 of 1513
Aug 12, 2011
(7) TAAn option register 0 (TAAnOPT0)
The TAAnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
TAAnCCS1
0
1
TAAnCCR1 register capture/compare selection
The TAAnCCS1 bit setting is valid only in the free-running timer mode.
Compare register selected
Capture register selected
TAAnOPT0
(n = 0 to 3, 5)
0
TAAnCCS1TAAnCCS0 0 0 0 TAAnOVF
654321
After reset: 00H R/W Address: TAA0OPT0 FFFFF635H, TAA1OPT0 FFFFF645H,
TAA2OPT0 FFFFF655H, TAA3OPT0 FFFFF665H,
TAA5OPT0 FFFFF685H
TAAnCCS0
0
1
TAAnCCR0 register capture/compare selection
The TAAnCCS0 bit setting is valid only in the free-running timer mode.
Compare register selected
Capture register selected
TAAnOVF
Set (1)
Reset (0)
TAAn overflow detection flag
• The TAAnOVF bit is set to 1 when the 16-bit counter count value overflows from
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
• An interrupt request signal (INTTAAnOV) is generated at the same time that the
TAAnOVF bit is set to 1. The INTTAAnOV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
• The TAAnOVF bit is not cleared even when the TAAnOVF bit or the TAAnOPT0
register are read when the TAAnOVF bit = 1.
• The TAAnOVF bit can be both read and written, but the TAAnOVF bit cannot be
set to 1 by software. Writing 1 has no influence on the operation of TAAn.
Overflow occurred
0 written to TAAnOVF bit or TAAnCTL0.TAAnCE bit = 0
7 0
Cautions 1. Rewrite the TAAnCCS1 and TAAnCCS0 bits when the
TAAnCE bit = 0. (The same value can be written when the
TAAnCE bit = 1.) If rewriting was mistakenly performed,
clear the TAAnCE bit to 0 and then set the bits again.
2. Be sure to set bits 1 to 3, 6, and 7 to “0”.