Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 219 of 1513
Aug 12, 2011
(2) TAAn control register 1 (TAAnCTL1)
The TAAnCTL1 register is an 8-bit register that controls the operation of TAAn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(1/2)
TAAnEST
0
1
Software trigger control (n = 0 to 3, 5)
After reset: 00H R/W Address:
Generates a valid signal for external trigger input.
• In one-shot pulse output mode:
A one-shot pulse is output with writing 1 to the TAAnEST bit as the trigger.
• In external trigger pulse output mode:
A PWM waveform is output with writing 1 to the TAAnEST bit as the trigger.
−
Tuned operation mode enable control
(m = 0, 2, 4, 5)
Tuned-operation function (specification of slave operation)
Simultaneous-start function (specification of slave timer)
Independent operation mode (asynchronous operation mode)
Setting prohibited
For the tuned-operation function, see 7.6 Timer-Tuned Operation Function.
For the simultaneous-start function, see 7.7 Simultaneous-Start Function.
TAA0SYE
TAA0CTL1 TAA0EST TAA0EEETAA0SYM 0 TAA0MD2 TAA0MD1 TAA0MD0
TAA2SYE
TAA2CTL1 TAA2EST TAA2EEETAA2SYM 0 TAA2MD2 TAA2MD1 TAA2MD0
TAA5SYE
TAA5CTL1 TAA5EST TAA5EEETAA5SYM 0 TAA5MD2 TAA5MD1 TAA5MD0
0
TAA1CTL1 TAA1EST TAA1EEE 0 0 TAA1MD2 TAA1MD1 TAA1MD0
TAA4SYE
TAA4CTL1 0 0 TAA4SYM 0 TAA4MD2 TAA4MD1 TAA4MD0
0
TAA3CTL1 TAA3EST TAA3EEE 0 0 TAA3MD2 TAA3MD1 TAA3MD0
65
4
3
1
TAA0CTL1 FFFFF631H, TAA1CTL1 FFFFF641H,
TAA2CTL1 FFFFF651H, TAA3CTL1 FFFFF661H,
TAA4CTL1 FFFFF671H, TAA5CTL1 FFFFF681H
7
0
2
TAAmSYE
0
0
1
1
TAA1
Master timer Slave timer
TAA3
TAB0
TAB1
TAA0
TAA2
TAA5
TAA4
TAAmSYM
0
1
0
1
These bits can be set only for the slave timer (setting them for the master timer is
prohibited).
The relationship between the master timer and slave timer is as follows.
Cautions 1. The TAAnEST bit is valid only in the external trigger pulse output
mode or one-shot pulse output mode. In any other mode, writing 1
to this bit is ignored.
2. Be sure to clear the sections of the TAAnCTL1 register of each
channel, where 0 is specified, to 0.