Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 209 of 1513
Aug 12, 2011
6.5 PLL Function
6.5.1 Overview
In the V850ES/JG3-H and V850ES/JH3-H, an operating clock that is 8 times higher than the oscillation frequency
output by the PLL function or the clock-through mode can be selected as the operating clock of the CPU and on-chip
peripheral functions.
When PLL function is used (×8): Input clock = 3.0 to 6.0 MHz (output: 24 to 48 MHz)
Clock-through mode: Input clock = 3.0 to 6.0 MHz (output: 3.0 to 6.0 MHz)
6.5.2 Registers
(1) PLL control register (PLLCTL)
The PLLCTL register is an 8-bit register that controls the PLL function.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
0PLLCTL 0 0 0 00 SELPLL PLLON
PLL stopped
PLL operating
(After PLL operation starts, a lockup time is required for frequency stabilization)
PLLON
0
1
PLL operation stop register
Clock-through mode
PLL mode
SELPLL
0
1
CPU operation clock selection register
After reset: 01H R/W Address: FFFFF82CH
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Cautions 1. When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0 (clock-
through mode).
2. The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If not
(unlocked), "0" is written to the SELPLL bit if data is written to it.