Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 205 of 1513
Aug 12, 2011
(a) Example of setting main clock operation → subclock operation
<1> CK3 bit ← 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to
CK0 bits.
<2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following
time after the CK3 bit is set until subclock operation is started.
Max.: 1/f
XT (1/subclock frequency)
<3> MCK bit ← 1: Set the MCK bit to 1 only when stopping the main clock.
Cautions 1. When stopping the main clock, stop the PLL. Also stop the operations of the on-chip
peripheral functions operating with the main clock.
2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the
conditions are satisfied, then change to the subclock operation mode.
Internal system clock (f
CLK) > Subclock (fXT: 32.768 kHz) × 4
Remark Internal system clock (f
CLK): Clock generated from the main clock (fXX) by setting the CK2 to CK0
bits
[Description example]
_DMA_DISABLE:
clrl 0, DCHCn[r0] -- DMA operation disabled. n = 0 to 3
<1> _SET_SUB_RUN :
st.b r0, PRCMD[r0]
set1 3, PCC[r0] -- CK3 bit ← 1
<2> _CHECK_CLS :
tst1 4, PCC[r0] -- Wait until subclock operation starts.
bz _CHECK_CLS
<3> _STOP_MAIN_CLOCK :
st.b r0, PRCMD[r0]
set1 6, PCC[r0] -- MCK bit ← 1, main clock is stopped.
_DMA_ENABLE:
setl 0, DCHCn[r0] -- DMA operation enabled. n = 0 to 3
Remark The description above is simply an example. Note that in <2> above, the CLS bit is read in a closed
loop.