Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 202 of 1513
Aug 12, 2011
(1) Main clock oscillator
The main clock oscillator oscillates the following frequencies (f
X).
• In clock-through mode
f
X = 3.0 to 6.0 MHz
• In PLL mode
f
X = 3.0 to 6.0 MHz (×8)
(2) Subclock oscillator
The sub-resonator oscillates a frequency of 32.768 kHz (f
XT).
(3) Main clock oscillator stop control
This circuit generates a control signal that stops oscillation of the main clock oscillator.
Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only when
the PCC.CLS bit = 1).
(4) Internal oscillator
Oscillates a frequency (f
R) of 220 kHz (TYP.).
(5) Prescaler 1
This prescaler generates the clock (f
XX to fXX/1,024) to be supplied to the following on-chip peripheral functions:
TAA, TAB, TMM, TMT, CSIF, UARTC, I
2
C, CAN, ADC, DAC, WDT2
(6) Prescaler 2
This circuit divides the main clock (f
XX).
The clock generated by prescaler 2 (fXX to fXX/32) is supplied to the selector that generates the CPU clock (fCPU)
and internal system clock (f
CLK).
f
CLK is the clock supplied to the INTC, ROM, and RAM blocks, and can be output from the CLKOUT pin.
(7) Prescaler 3
This circuit divides the clock generated by the main clock oscillator (f
X) to a specific frequency (32.768 kHz) and
supplies that clock to the real-time counter (RTC) block.
(8) PLL
This circuit multiplies the clock generated by the main clock oscillator (f
X) by 8.
It operates in two modes: clock-through mode in which f
X is output as is, and PLL mode in which a multiplied clock
is output. These modes can be selected by using the PLLCTL.SELPLL bit.