Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 201 of 1513
Aug 12, 2011
6.2 Configuration
Figure 6-1. Clock Generator
CLKOUT
UCLK
f XX /32
f
XX /16
f
XX /8
f
XX /4
f
XX /2
f XX
f CPU
f CLK
f XT
f XT
f R
Selector
Selector
Selector
FRC bit
MFRC
bit
SELPLL bit
PLLON
bit
CLS, CK3
bits
CK2 to CK0
bits
UCKSEL
bit
STOP mode
Subclock
oscillator
RTC clock,
WDT clock
RTC clock
Port CM
Prescaler 1
Prescaler 2
IDLE
control
HALT
mode
CPU clock
Peripheral clock
USB clock
WDT clock,
TMM clock
Internal
system clock
Prescaler 3
Main clock
oscillator
Main clock
oscillator
stop control
RSTOP bit
Internal
oscillator
1/8 divider
XT1
XT2
X1
X2
IDLE mode
PLL
f
XX
f X
IDLE
control
Selector
Selector
HALT
control
Remark fX: Main clock oscillation frequency
f
XX: Main clock frequency
f
CLK: Internal system clock frequency
fXT: Subclock frequency
f
CPU: CPU clock frequency
f
R: Internal oscillation clock frequency