Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 200 of 1513
Aug 12, 2011
CHAPTER 6 CLOCK GENERATION FUNCTION
6.1 Overview
The following clock generation functions are available.
Main clock oscillator
• In clock-through mode
f
X = 3.0 to 6.0 MHz (fXX = 3.0 to 6.0 MHz)
• In PLL mode
f
X = 3.0 to 6.0 MHz (×8: fXX = 24 to 48 MHz)
Subclock oscillator
• fXT = 32.768 kHz
Multiply (×8) function by PLL (Phase Locked Loop)
• Clock-through mode/PLL mode selectable
Internal oscillator
• f
R = 220 kHz (TYP.)
Internal system clock generation
• 7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
Peripheral clock generation
Clock output function
Remark f
X: Main clock oscillation frequency
f
XX: Main clock frequency
fXT: Subclock frequency
f
R: Internal oscillation clock frequency