Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 199 of 1513
Aug 12, 2011
Figure 5-8. Multiplexed/Separate Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) (V850ES/JH3-H only)
T1
A1
A1
A2
UndefinedUndefined
Undefined
T2 T3 TI
Note 1
TH TH TH TH TI
Note 1
T1 T2 T3
D1
CLKOUT
HLDRQ
HLDAK
A23 to A0
ASTB
AD15 to AD0
RD
A2 D2
1111 1111
CS3, CS2, CS0
Note 2
Undefined
Notes 1. This idle state (TI) does not depend on the BCC register settings.
2. Only the CS space subject to access is active.
Remarks 1. See Table 2-2 for the pin statuses in the bus hold mode.
2. The broken lines indicate high impedance.