Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 198 of 1513
Aug 12, 2011
Figure 5-6. Multiplexed/Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access)
A1
11
00
11 11
00
11
A2
A3
D1
D2
A3A2
A1
T2 T3 T1T1 T2 TW TW T3 T1
CLKOUT
A23 to A0
Note 1
ASTB
WAIT
AD15 to AD0
WR1, WR0
WR1, WR0
01
10
CS3, CS2, CS0
Note 2
AD15 to AD8
AD7 to AD0
Undefined
Hi-Z
Active
Active
Odd Address Even Address8-bit Access
Programmable
wait
External
wait
Notes 1. V850ES/JH3-H only
2. Only the CS space subject to access is active.
Figure 5-7. Multiplexed/Separate Bus Write Timing (Bus Size: 8 Bits)
A1
11 10 11 11 10 11
A2
A3
D1
D2
A3A2
A1
T2 T3 T1T1 T2 TW TW T3 T1
CLKOUT
A23 to A0
Note 1
,
AD15 to AD8
ASTB
WAIT
AD7 to AD0
WR1, WR0
CS3, CS2, CS0
Note 2
Programmable
wait
External
wait
Notes 1. V850ES/JH3-H only
2. Only the CS space subject to access is active.