Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 197 of 1513
Aug 12, 2011
5.9 Bus Timing
Figure 5-4. Multiplexed/Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access)
A1
A2
A3
D1
D2
A3A2
A1
T1 T2 T3 T1 T2 TW TW T3 TI T1
CLKOUT
A23 to A0
Note 1
ASTB
CS3, CS2, CS0
Note 2
WAIT
AD15 to AD0
RD
AD15 to AD8
AD7 to AD0
Hi-Z
Hi-Z
Active
Active
Odd Address Even Address8-bit Access
Programmable
wait
External
wait
Idle state
Notes 1. V850ES/JH3-H only
2. Only the CS space subject to access is active.
Remark The broken lines indicate high impedance.
Figure 5-5. Multiplexed/Separate Bus Read Timing (Bus Size: 8 Bits)
A1
A2
A3
D1
D2
A3A2
A1
T1 T2 T3 T1 T2 TW TW T3 TI T1
CLKOUT
A23 to A0
Note 1
,
AD15 to AD8
ASTB
WAIT
AD7 to AD0
RD
CS3, CS2, CS0
Note 2
Programmable
wait
External
wait
Idle state
Notes 1. V850ES/JH3-H only
2. Only the CS space subject to access is active.
Remark The broken lines indicate high impedance.