Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 192 of 1513
Aug 12, 2011
5.5.4 Programmable address wait function
Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address
wait insertion is set for each chip select area (CS0, CS2, CS3).
If an address setup wait is inserted, it seems that the high-clock period of the T1 state is extended by 1 clock. If an
address-hold wait is inserted, it seems that the low-clock period of the T1 state is extended by 1 clock.
(1) Address wait control register (AWC)
The AWC register can be read or written in 16-bit units.
Reset sets this register to FFFFH.
Cautions 1. Address-setup wait and address-hold wait cycles are not inserted when the internal ROM area,
internal RAM area, and on-chip peripheral I/O areas are accessed.
2. Write to the AWC register after reset, and then do not change the set values. Also, do not
access an external memory area until the initial settings of the AWC register are complete.
After reset: FFFFH R/W Address: FFFFF488H
1
AHW3
AHWn
0
1
Not inserted
Inserted
AWC 1
ASW3
1
AHW2
1
ASW2
1
AHW1
Note
1
ASW1
Note
1
AHW0
1
ASW0
8
910
11
1213
Specifies insertion of address-hold wait (n = 0 to 3)
1415
1234567 0
ASWn
0
1
Not inserted
Inserted
Specifies insertion of address-setup wait (n = 0 to 3)
CS0
CS3
CS2
Note It is recommended to clear the AHW1 bit and the ASW1 bit to 0.
Caution Be sure to set bits 15 to 8 to “1”.