Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 189 of 1513
Aug 12, 2011
5.5 Wait Function
5.5.1 Programmable wait function
(1) Data wait control register 0 (DWC0)
To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle
that is executed for each CS space.
The number of wait states can be programmed by using the DWC0 register. Immediately after system reset, 7 data
wait states are inserted for all the blocks.
The DWC0 register can be read or written in 16-bit units.
Reset sets this register to 7777H.
Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are
always accessed without a wait state. The on-chip peripheral I/O area is also not subject to
programmable wait, and only wait control from each peripheral function is performed.
2. Write to the DWC0 register after reset, and then do not change the set values. Also, do not
access an external memory area until the initial settings of the DWC0 register are complete.
After reset: 7777H R/W Address: FFFFF484H
0
0
DWn2
0
0
0
0
1
1
1
1
DWn1
0
0
1
1
0
0
1
1
DWn0
0
1
0
1
0
1
0
1
None
1
2
3
4
5
6
7
DWC0 DW32
DW12
Note
DW31
DW11
Note
DW30
DW10
Note
0
0
DW22
DW02
DW21
DW01
DW20
DW00
8
910
11
1213
Number of wait states inserted in
CSn space (n = 0 to 3)
1415
1234567 0
CS0
CS3
CS2
Note The DW12 to DW10 bits set wait of access to the USB function area.
It is recommended to set the DW12 to DW10 bits to 001B (1 wait).
Caution Be sure to clear bits 15, 11, 7, and 3 to “0”.