Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 181 of 1513
Aug 12, 2011
5.4 Bus Access
5.4.1 Number of clocks for access
The following table shows the number of basic clocks required for accessing each resource.
External Memory (16 Bits)
Area (Bus Width)
Bus Cycle Type
Internal ROM (32 Bits) Internal RAM (32 Bits)
Multiplexed Separate
Note 1
Instruction fetch (normal access) 1 1
Note 2
3 + n
Instruction fetch (branch) 3 2
Note 1
3 + n
Operand data access 5 1 3 + n
Notes 1. V850ES/JH3-H only
2. Increases by 1 if a conflict with a data access occurs.
Remark Unit: Clocks/access
5.4.2 Bus size setting function
Each external memory area selected by memory block CSn can be set by using the BSC register. However, the bus
size can be set to 8 bits and 16 bits only.
The external memory area of the V850ES/JG3-H and V850ES/JH3-H is selected by memory blocks CS0, CS2, and
CS3.
(1) Bus size configuration register (BSC)
The BSC register can be read or written in 16-bit units.
Reset sets this register to 5555H.
Caution Write to the BSC register after reset, and then do not change the set values. Also, do not access
an external memory area until the initial settings of the BSC register are complete.
After reset: 5555H R/W Address: FFFFF066H
0
0
BSn0
0
1
8 bits
16 bits
BSC 1
BS30
0
0
1
BS20
0
0
1
1
0
0
1
BS00
8
910
11
1213
Data bus width of memory block CSn space (n = 0, 2, 3)
1415
1234567 0
CS0
CS3
CS2
Caution Be sure to set bits 14, 12, 10, 8, and 2 to “1”, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to “0”.