Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 180 of 1513
Aug 12, 2011
5.3 Memory Block Function
The 16 MB external memory space is divided into memory blocks of 2 MB, 4 MB, and 8 MB from the lowest of the
memory space. The programmable wait function and bus cycle operation mode for each of these blocks can be
independently controlled in one-block units.
Figure 5-1. Data Memory Map: Physical Address
CS2
CS3
(CS1
Note 1
)
CS0
(80 KB)
Use prohibited
Use prohibited
Note 2
Use prohibited
Use prohibited
USB function area
Data-only RAM area
Programmable peripheral
I/O area
Note 3
or use prohibited
Note 4
External memory area
(8 MB)
External memory area
(4 MB)
External memory area
(2 MB)
(2 MB)
Internal ROM area
Note 5
(1 MB)
External memory area
(1 MB)
Internal RAM area
(60 KB)
On-chip peripheral
I/O area (4 KB)
03FFFFFFH
03FEC000H
03FEBFFFH
01000000H
00FFFFFFH
00800000H
007FFFFFH
00400000H
003FFFFFH
00200000H
001FFFFFH
00000000H
03FFFFFFH
003FFFFFH
00300000H
002FFFFFH
00280000H
0027FFFFH
00250000H
0024FFFFH
00200000H
001FFFFFH
00100000H
000FFFFFH
00000000H
03FFF000H
03FFEFFFH
03FF0000H
03FEFFFFH
03FEF000H
03FEEFFFH
03FEC000H
Notes 1. CS1 is not provided as an external signal of the V850ES/Jx3-H; it is used internally as a chip select
signal for the USB.
2. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because these addresses are in the
same area as the on-chip peripheral I/O area.
3. Only the programmable peripheral I/O area is seen as images of 256 MB each in the 4 GB address
space.
4. In the CAN controller version, addresses 03FEC000H to 03FEEFFFH are assigned as a
programmable peripheral I/O area in addresses 03FEC000H to 03FECBFFH. Use of these
addresses in a version without a CAN controller is prohibited.
5. This area is an external memory area in the case of a data write access.