Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 179 of 1513
Aug 12, 2011
5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed
When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows.
Table 5-4. Pin Statuses When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
Separate Bus Mode Multiplexed Bus Mode Bus Control Pin
Internal ROM/RAM Peripheral I/O Internal ROM/RAM Peripheral I/O
Address/data bus
(AD15 to AD0)
Undefined Undefined Undefined Undefined
Address bus
(A23 to A16)
Undefined Undefined (Address
output during access)
Undefined Undefined (Address
output during access)
Address bus
(A15 to A0)
Undefined Undefined (Address
output during access)
Undefined Undefined (Address
output during access)
Control signal Inactive Inactive Inactive Inactive
Caution When a write access is performed to the internal ROM area, address, data, and control signals are
activated in the same way as access to the external memory area.
5.2.2 Pin status in each operation mode
For the pin status of the V850ES/JG3-H and V850ES/JH3-H in each operation mode, see 2.2 Pin States.