Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 178 of 1513
Aug 12, 2011
5.2 Bus Control Pins
The pins used to connect an external device are listed in the table below.
Table 5-1. V850ES/JH3-H Bus Control Pins (Multiplexed Bus)
Bus Control Pin Alternate-Function Pin I/O Function
AD0 to AD15 PDL0 to PDL15 I/O Address/data bus
A16 to A23 PDH0 to PDH7 Output Address bus
WAIT PCM0 Input External wait control
CLKOUT PCM1 Output Internal system clock
WR0, WR1 PCT0, PCT1 Output Write strobe signal
RD PCT4 Output Read strobe signal
ASTB PCT6 Output Address strobe signal
HLDRQ PCM3 Input
HLDAK PCM2 Output
Bus hold control
CS0, CS2, CS3 PCS0, PCS2, PCS3 Output Chip select
Table 5-2. V850ES/JH3-H Bus Control Pins (Separate Bus)
Bus Control Pin Alternate-Function Pin I/O Function
AD0 to AD15 PDL0 to PDL15 I/O Data bus
A0 to A15 P90 to P915 Output Address bus
A16 to A23 PDH0 to PDH7 Output Address bus
WAIT PCM0 Input External wait control
CLKOUT PCM1 Output Internal system clock
WR0, WR1 PCT0, PCT1 Output Write strobe signal
RD PCT4 Output Read strobe signal
HLDRQ PCM3 Input
HLDAK PCM2 Output
Bus hold control
CS0, CS2, CS3 PCS0, PCS2, PCS3 Output Chip select
Table 5-3. V850ES/JG3-H Bus Control Pins (Multiplexed Bus)
Bus Control Pin Alternate-Function Pin I/O Function
AD0 to AD15 PDL0 to PDL15 I/O Address/data bus
WAIT PCM0 Input External wait control
CLKOUT PCM1 Output Internal system clock
WR0, WR1 PCT0, PCT1 Output Write strobe signal
RD P61 Output Read strobe signal
ASTB P62 Output Address strobe signal
CS0, CS2, CS3 P63, P64, P65 Output Chip select