Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS
R01UH0042EJ0500 Rev.5.00 Page 176 of 1513
Aug 12, 2011
4.5.3 Cautions on on-chip debug pins (V850ES/JG3-H only)
The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins.
After reset by the RESET pin, the P56/INTP05/DRST pin is initialized to function as an on-chip debug pin (DRST). If a
high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can
be used.
The following action must be taken if on-chip debugging is not used.
• Clear the OCDM0 bit of the OCDM register (special register) (0)
At this time, fix the P56/INTP05/DRST pin to low level from when reset by the RESET pin is released until the above
action is taken.
If a high level is input to the DRST pin before the above action is taken, it may cause a malfunction (CPU deadlock).
Handle the P56 pin with the utmost care.
Caution After reset by the WDT2RES signal, clock monitor (CLM), or low-voltage detector (LVI), the
P56/INTP05/DRST pin is not initialized to function as an on-chip debug pin (DRST). The OCDM
register holds the current value.
4.5.4 Cautions on P56/INTP05/DRST pin
The P56/INTP05/DRST pin has an internal pull-down resistor (30 kΩ TYP.). After a reset by the RESET pin, a pull-
down resistor is connected. The pull-down resistor is disconnected when the OCDM0 bit is cleared (0).
4.5.5 Cautions on P10, P11, and P53 pins when power is turned on
When the power is turned on, the following pins may output an undefined level temporarily even during reset.
• P10/ANO0 pin
• P11/ANO1 pin
• P53/SIF2/TIAB00/KR3/TOAB00/RTP03/DDO pin (V850ES/JG3-H only)
4.5.6 Hysteresis characteristics
In port mode, the following port pins do not have hysteresis characteristics.
P00 to P05
P20 to P25
P30 to P37
P40 to P42
P50 to P56
P60 to P65
P90 to P915