Datasheet

V850ES/JG3-H, V850ES/JH3-H APPENDIX D INSTRUCTION SET LIST
R01UH0042EJ0500 Rev.5.00 Page 1505 of 1513
Aug 12, 2011
Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1
field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and
in the opcode differs from other instructions.
rrrrr = regID specification
RRRRR = reg2 specification
13. iiiii: Lower 5 bits of imm9.
IIII: Higher 4 bits of imm9.
14. Do not specify the same register for general-purpose registers reg1 and reg3.
15. sp/imm: Specified by bits 19 and 20 of the sub-opcode.
16. ff = 00: Load sp in ep.
01: Load sign-expanded 16-bit immediate data (bits 47 to 32) in ep.
10: Load 16-bit logically-left-shifted 16-bit immediate data (bits 47 to 32) in ep.
11: Load 32-bit immediate data (bits 63 to 32) in ep.
17. If imm = imm32, n + 3 clocks.
18. rrrrr: Other than 00000.
19. ddddddd: Higher 7 bits of disp8.
20. dddd: Higher 4 bits of disp5.
21. dddddd: Higher 6 bits of disp8.