Datasheet
V850ES/JG3-H, V850ES/JH3-H APPENDIX D INSTRUCTION SET LIST
R01UH0042EJ0500 Rev.5.00 Page 1501 of 1513
Aug 12, 2011
(3/6)
Execution
Clock
Flags Mnemonic Operand Opcode Operation
i r l CY OV S Z SAT
LD.H disp16[reg1],reg2 rrrrr111001RRRRR
ddddddddddddddd0
Note 8
adr←GR[reg1]+sign-extend(disp16)
GR[reg2]←sign-extend(Load-memory(adr,Halfword))
11
Note
11
Other than regID = PSW 1 1 1 LDSR reg2,regID rrrrr111111RRRRR
0000000000100000
Note 12
SR[regID]←GR[reg2]
regID = PSW 1 1 1 × × × × ×
LD.HU disp16[reg1],reg2 rrrrr1 11111RRRRR
ddddddddddddddd1
Note 8
adr←GR[reg1]+sign-extend(disp16)
GR[reg2]←zero-extend(Load-memory(adr,Halfword)
11
Note
11
LD.W disp16[reg1],reg2 rrrrr1 11001RRRRR
ddddddddddddddd1
Note 8
adr←GR[reg1]+sign-extend(disp16)
GR[reg2]←Load-memory(adr,Word)
11
Note
11
reg1,reg2 rrrrr 000000RRRRR GR[reg2]←GR[reg1] 1 1 1
imm5,reg2 r r r r r 0 1 0 000iiiii GR[reg2]←sign-extend(imm5) 1 1 1
MOV
imm32,reg1 00000110001RRRRR
iiiiiiiiiiiiiiii
IIIIIIIIIIIIIIII
GR[reg1]←imm32 2 2 2
MOVEA imm16,reg1,reg2 rrrrr110 001RRRRR
iiiiiiiiiiiiiiii
GR[reg2]←GR[reg1]+sign-extend(imm16) 1 1 1
MOVHI imm16,reg1,reg2 rrrrr110 010RRRRR
iiiiiiiiiiiiiiii
GR[reg2]←GR[reg1]+(imm16 ll 0
16
) 1 1 1
reg1,reg2,reg3 rrrr r111111 RRRRR
wwwww01000100000
GR[reg3] ll GR[reg2]←GR[reg2]xGR[reg1]
Note 14
14 5 MUL
imm9,reg2,reg3 rrrrr111111iiiii
wwwww01001IIII00
Note 13
GR[reg3] ll GR[reg2]←GR[reg2]xsign-extend(imm9) 14 5
reg1,reg2 rrrrr 000111RRRRR
GR[reg2]←GR[reg2]
Note 6
xGR[reg1]
Note 6
11 2
MULH
imm5,reg2 r r r r r 0 1 0 111iiiii
GR[reg2]←GR[reg2]
Note 6
xsign-extend(imm5)
11 2
MULHI imm16,reg1,reg2 r r rrr1101 11RRRR R
iiiiiiiiiiiiiiii
GR[reg2]←GR[reg1]
Note 6
ximm16
11 2
reg1,reg2,reg3 rrrr r111111 RRRRR
wwwww01000100010
GR[reg3] ll GR[reg2]←GR[reg2]xGR[reg1]
Note 14
14 5 MULU
imm9,reg2,reg3 rrrrr111111iiiii
wwwww01001IIII10
Note 13
GR[reg3] ll GR[reg2]←GR[reg2]xzero-extend(imm9) 14 5
NOP 0000000000000000 Pass at least one clock cycle doing nothing. 1 1 1
NOT reg1,reg2 rrrrr000 001RRRRR GR[reg2]←NOT(GR[reg1]) 1 1 1 0 × ×
bit#3,disp16[reg1] 01bbb111110RRRRR
dddddddddddddddd
adr←GR[reg1]+sign-extend(disp16)
Z flag←Not(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,Z flag)
3
Note 3
3
Note 3
3
Note 3
×
NOT1
reg2,[reg1] rrrrr 111111RRRRR
0000000011100010
adr←GR[reg1]
Z flag←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,Z flag)
3
Note 3
3
Note 3
3
Note 3
×