Datasheet

V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX
R01UH0042EJ0500 Rev.5.00 Page 1475 of 1513
Aug 12, 2011
(17/37)
Symbol Name Unit Page
CF3CTL2 CSIF3 control register 2 CSIF 773
CF3RIC Interrupt control register INTC 1264
CF3RX CSIF3 receive data register CSIF 767
CF3RXL CSIF3 receive data register L CSIF 767
CF3STR CSIF3 status register CSIF 775
CF3TIC Interrupt control register INTC 1265
CF3TX CSIF3 transmit data register CSIF 768
CF3TXL CSIF3 transmit data register L CSIF 768
CF4CTL0 CSIF4 control register 0 CSIF 769
CF4CTL1 CSIF4 control register 1 CSIF 772
CF4CTL2 CSIF4 control register 2 CSIF 773
CF4RIC Interrupt control register INTC 1264
CF4RX CSIF4 receive data register CSIF 767
CF4RXL CSIF4 receive data register L CSIF 767
CF4STR CSIF4 status register CSIF 775
CF4TIC Interrupt control register INTC 1264
CF4TX CSIF4 transmit data register CSIF 768
CF4TXL CSIF4 transmit data register L CSIF 768
CKC Clock control register CG 210
CLM Clock monitor mode register CLM 1337
CPUBCTL CPU I/F bus control register USBF 1169
CRCD CRC data register CRC 1349
CRCIN CRC input register CRC 1349
CTBP CALLT base pointer CPU 62
CTPC CALLT execution status saving register CPU 61
CTPSW CALLT execution status saving register CPU 61
DA0CS0 D/A conversion value setting register 0 DAC 717
DA0CS1 D/A conversion value setting register 1 DAC 717
DA0M D/A converter mode register DAC 716
DADC0 DMA addressing control register 0 DMAC 1237
DADC1 DMA addressing control register 1 DMAC 1237
DADC2 DMA addressing control register 2 DMAC 1237
DADC3 DMA addressing control register 3 DMAC 1237
DBC0 DMA transfer count register 0 DMAC 1236
DBC1 DMA transfer count register 1 DMAC 1236
DBC2 DMA transfer count register 2 DMAC 1236
DBC3 DMA transfer count register 3 DMAC 1236
DBPC Exception/debug trap status saving register CPU 62
DBPSW Exception/debug trap status saving register CPU 62
DCHC0 DMA channel control register 0 DMAC 1238
DCHC1 DMA channel control register 1 DMAC 1238
DCHC2 DMA channel control register 2 DMAC 1238