Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS
R01UH0042EJ0500 Rev.5.00 Page 1442 of 1513
Aug 12, 2011
(12) RAM retention detection
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VRAMH 1.9 2.0 2.1 V
Supply voltage rise time tRAMHTH VDD = 0 to 2.85 V 0.002 ms
Response time
Note
tRAMHD After VDD reaches 2.1 V 0.2 3.0 ms
Minimum pulse width tRAMHW 0.2 ms
Note Time required to detect the detection voltage and set the RAMS.RAMF bit.
Supply voltage
(V
DD )
Time
Detection voltage (MIN.)
RAMS.RAMF bit
Cleared by instruction
Operating voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t RAMHW
t RAMHD t RAMHD
t RAMHTH