Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS
R01UH0042EJ0500 Rev.5.00 Page 1441 of 1513
Aug 12, 2011
(10) D/A converter
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, 3.0 V ≤ AVREF1 ≤ 3.6 V, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 8 bit
Overall error
Note 1
R = 2 MΩ ±1.2 %FSR
Settling time C = 20 pF 3 μ s
Output resistor RO Output data 55H 6.42 kΩ
Reference voltage AVREF1 3.0 3.6 V
D/A conversion operating 1 2.5 mA AVREF1 current
Note 2
AIREF1
D/A conversion stopped 5
μ A
Notes 1. Excluding quantization error (±0.5 %LSB).
2. Value of 1 channel of D/A converter
Remark R is the output pin load resistance and C is the output pin load capacitance.
(11) LVI circuit characteristics
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VLVI0 2.85 2.95 3.05 V
Response time
Note
tLD After VDD reaches VLVI0 (MAX.), or after VDD
has dropped to VLVI0 (MAX.)
0.2 2.0 ms
Minimum pulse width tLW 0.2 ms
Reference voltage
stabilization wait time
tLWAIT After VDD reaches 2.85 V(MIN.) 0.1 0.2 ms
Note Time required to detect the detection voltage and output an interrupt or reset signal.
Supply voltage
(V
DD )
Time
Detection voltage (MIN.)
Operating voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t LWAIT
t LW
t LD t LD
LVION bit = 0 → 1