Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS
R01UH0042EJ0500 Rev.5.00 Page 1440 of 1513
Aug 12, 2011
(8) High-impedance control timing
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Time from oscillator stop to timer output high impedance tCLM Clock monitor
operating
65 μ s
Time from TOAB1OFF input → timer output high impedance tHTQn 300 ns
Time from TOAA1OFF input → timer output high impedance tHTP2 300 ns
(9) A/D converter
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, 3.0 V ≤ AVREF0 ≤ 3.6 V, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 bit
Overall error
Note
3.0 ≤ AVREF0 ≤ 3.6 V ±0.6 %FSR
Conversion time tCONV 2.17 24 μs
Zero scale error ±0.5 %FSR
Full scale error ±0.5 %FSR
Non-linearity error ±4.0 LSB
Differential linearity error ±4.0 LSB
Analog input voltage VIAN AVSS AVREF0 V
Reference voltage AVREF0 3.0 3.6 V
Normal conversion mode 3 6.5 mA
High-speed conversion mode 4 10 mA
AVREF0 current AIREF0
When A/D converter unused 5
μ A
Note Excluding quantization error (±0.05 %FSR).
Caution Do not set (read/write) alternate-function ports during A/D conversion; otherwise the conversion
resolution may be degraded.
Remark LSB: Least Significant Bit
FSR: Full Scale Range