Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS
R01UH0042EJ0500 Rev.5.00 Page 1435 of 1513
Aug 12, 2011
(b) Slave mode
[When using CSI0 to CSIF2, or CSIF4]
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
SCKFn cycle time tKCY2 <63> 125 ns
SCKFn high-level width tKH2 tKCYn/2 − 8 ns
SCKFn low-level width tKL2
<64>
tKCYn/2 − 8 ns
SIFn setup time (to SCKFn↑) 27 ns
SIFn setup time (from SCKFn↓)
t
SIK2 <65>
27 ns
SIFn hold time (to SCKFn↑) 27 ns
SIFn hold time (from SCKFn↓)
t
KSI2 <66>
27 ns
SOFn output delay time (to SCKFn↑) 27 ns
SOFn output delay time (from SCKFn↓)
t
KSO2 <67>
27 ns
SOFn output delay time (to SCKFn↑) tKCYn/2 − 10 ns
SOFn output delay time (from SCKFn↓)
t
HSO2 <68>
t
KCYn/2 − 10 ns
Remark n = 0 to 4