Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS
R01UH0042EJ0500 Rev.5.00 Page 1434 of 1513
Aug 12, 2011
(5) CSIF timing
(a) Master mode
[When using CSI0 to CSIF2, or CSIF4]
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
SCKFn cycle time tKCY1 <63> 125 ns
SCKFn high-level width tKH1 tKCY1/2 − 8 ns
SCKFn low-level width tKL1
<64>
tKCY1/2 − 8 ns
SIFn setup time (to SCKFn↑) 27 ns
SIFn setup time (to SCKFn↓)
t
SIK1 <65>
27 ns
SIFn hold time (from SCKFn↑) 27 ns
SIFn hold time (from SCKFn↓)
t
KSI1 <66>
27 ns
SOFn output delay time (from SCKFn↑) 27 ns
SOFn output delay time (from SCKFn↓)
t
KSO1 <67>
27 ns
SOFn output hold time (from SCKFn↑) tKCY1/2 − 10 ns
SOFn output hold time (from SCKFn↓)
t
HSO1 <68>
t
KCY1/2 − 10 ns
Remark n = 0 to 2, 4
[When using CSI3]
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
SCKF3 cycle time tKCYM <63> 83.3 ns
SCKF3 high-level width tKCYM/2 − 8 ns
SCKF3 low-level width
t
KHM <64>
t
KCYM/2 − 8 ns
SIF3 setup time (to SCKF3↑) 16 ns
SIF3 setup time (to SCKF3↓)
t
SIKM <65>
16 ns
SIF3 hold time (from SCKF3↑) 16 ns
SIF3 hold time (from SCKF3↓)
t
KSIM <66>
16 ns
SOF3 output delay time (from SCKF3↑) 16 ns
SOF3 output delay time (from SCKF3↓)
t
KSOM <67>
16 ns
SOF3 output hold time (from SCKF3↑) tKCYM/2 − 10 ns
SOF3 output hold time (from SCKF3↓)
t
HSOM <68>
t
KCYM/2 − 10 ns