Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS
R01UH0042EJ0500 Rev.5.00 Page 1431 of 1513
Aug 12, 2011
(2) Reset, interrupt timing
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
RESET input low-level width tWRSL 500 ns
NMI high-level width tWNIH Analog noise elimination 500 ns
NMI low-level width tWNIL Analog noise elimination 500 ns
n = 0 to 18 (Analog noise elimination) 500 ns INTPn high-level width tWITH
n = 2 (Digital noise elimination) 3T
SMP + 20 ns
n = 0 to 18 (Analog noise elimination) 500 ns INTPn low-level width tWITL
n = 2 (Digital noise elimination) 3T
SMP + 20 ns
Remark TSMP: Set by the noise elimination control register (INTNFC). Selectable from fXX/64, fXX/128, fXX/256, fXX/512,
and f
XX/1024.
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
KRn high-level width tWKRH Analog noise elimination 500 ns
KRn low-level width tWKRL Analog noise elimination 500 ns
Remark n = 0 to 7