Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS
R01UH0042EJ0500 Rev.5.00 Page 1430 of 1513
Aug 12, 2011
33.8 Basic Operation
(1) Power on/power off/reset timing
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Time from EVDD, UVDD↑ to VDD↑ tREL <56> 0 ns
Time from EVDD, UVDD↑ to AVREF0, AVREF1↑ tREA <57> 0 tREL ns
Time from VDD↑ to RESET↑ tRER <58> 500 +
t
REG
Note
ns
Analog noise elimination (during
flash erase/writing)
500 ns RESET low-level width tWRSL <59>
Analog noise elimination 500 ns
Time from RESET↓ to VDD↓ tFRE <60> 500 ns
Time from VDD↓ to EVDD, UVDD↓ tFEL <61> 0 ns
Time from AVREF0, AVREF1↓ to EVDD, UVDD↓ tFEA <62> 0 tFEL ns
Note Depends on the on-chip regulator characteristics.
V DD
EV DD , UV DD
V I V I V I V I
AV REF0 , AV REF1
RESET (input)
<56>
<58>
<60><59>
<57>
<61>
<62>