Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS
R01UH0042EJ0500 Rev.5.00 Page 1428 of 1513
Aug 12, 2011
(2) During bus hold (V850ES/JH3-H only)
(a) CLKOUT asynchronous
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
HLDRQ high-level width tWHQH <44> T + 16 ns
HLDAK low-level width tWHAL <45> T − 10 ns
Delay time from HLDAK↑ to bus output tDHAC <46> −7 ns
Delay time from HLDRQ↓ to HLDAK↓ tDHQHA1 <47> 2.5T ns
Delay time from HLDRQ↑ to HLDAK↑ tDHQHA2 <48> 0.5T + 17 1.5T + 31 ns
Delay time from bus float to HLDAK↓ tDFHA <49> 0 ns
Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency)
2. n: Number of wait clocks inserted in the bus cycle
The sampling timing changes when a programmable wait is inserted.
3. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
Bus Hold (CLKOUT Asynchronous)
CLKOUT (output)
HLDRQ (input)
HLDAK (output)
Address bus (output)
Data bus (I/O)
TH TH THTI TI
Hi-Z
CS0, CS2,
CS3 (output)
Hi-Z
ASTB (output)
RD (output),
WR0, WR1 (output)
Hi-Z
Hi-Z
<44>
<48>
<45>
<49>
<46>
<47>