Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS
R01UH0042EJ0500 Rev.5.00 Page 1426 of 1513
Aug 12, 2011
(b) Read/write cycle (CLKOUT synchronous): In multiplexed bus mode/separate bus mode
(TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Delay time from CLKOUT↑ to address tDKA <33> 0 17 ns
Delay time from CLKOUT↑ to address float tFKA <34> 0 15 ns
Delay time from CLKOUT↓ to ASTB tDKST <35> 0 12 ns
Delay time from CLKOUT↑ to RD, WRm tDKRDWR <36> 0 12 ns
Data input setup time (to CLKOUT↑) tSIDK <37> 16 ns
Data input hold time (from CLKOUT↑) tHKID <38> 0 ns
Data output delay time from CLKOUT↑ tDKOD <39> 17 ns
WAIT setup time (to CLKOUT↓) tSWTK <40> 16 ns
WAIT hold time (from CLKOUT↓) tHKWT <41> 0 ns
Address hold time from CLKOUT↑ tHKA2 <42> 0 ns
Data output hold time from CLKOUT↑ tHKOD2 <43> 0 ns
Remarks 1. m = 0, 1
2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
Read Cycle (CLKOUT Synchronous): In Multiplexed Bus Mode/Separate Bus Mode
CLKOUT (output)
A16 to A23 (output)
Note
AD0 to AD15 (I/O)
ASTB (output)
RD (output)
WAIT (input)
T1 T2 TW T3 Ti T1
DataAddress
Hi-Z
<33>
<35>
<36>
<34>
<42>
<35>
<42>
<36>
<40>
<40>
<41>
<41>
<37> <38>
CS0, CS2,
CS3 (output)
Note V850ES/JH3-H only
Remark WR0 and WR1 are high level.