Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS
R01UH0042EJ0500 Rev.5.00 Page 1423 of 1513
Aug 12, 2011
33.7.2 Bus timing
(1) In multiplexed bus mode/separate bus mode
(a) Read/write cycle (CLKOUT asynchronous)
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Address setup time (to ASTB↓) tDAST <6> (0.5 + tASw)T − 9 ns
Address hold time (from ASTB↓) tHSTA <7> (0.5 + tAHw)T − 8 ns
Delay time from RD↓ to address float tFRDA <8> 5 ns
Data input setup time from address tDAID <9> (2 + n + tASw + tAHw)T − 25 ns
Data input setup time from RD↓ tDRDID2 <10> (1 + n)T − 15 ns
Delay time from ASTB↓ to RD↓ tDSTRD
Delay time from ASTB↓ to WRm↓ tDSTWR
<11> (0.5 + t
AHw)T − 4 ns
Data input hold time (from RD↑) tHRDID <12> 0 ns
Address output delay time from RD↑ tDRDOD <13> (1 + i)T − 3 ns
Delay time from RD↑ to ASTB↑ tDRDST
Delay time from WRm↑ to ASTB↑ tDWRST
<14> 0.5T − 5 ns
Delay time from RD↑ to ASTB↓ tDRDST <15> (1.5 + i + tASw)T − 4 ns
RD low-level width tWRDL
WRm low-level width tWWRL
<16> (1 + n)T − 10 ns
ASTB high-level width tWSTH <17> (1 + i + tASw)T − 10 ns
Data output delay time from WRm↓ tDWROD <18> 9 ns
Data output delay time (from WRm↑) tDODWR <19> (1 + n)T − 11 ns
Data output hold time (from WRm↑) tHWROD <20> T − 3 ns
tSAWT1 <21> n ≥ 1 (1.5 + tASw + tAHw)T − 25 ns WAIT setup time (to address)
t
SAWT2 <22> (1.5 + n + tASw + tAHw)T − 25 ns
tHAWT1 <23> n ≥ 1 (0.5 + n + tASw + tAHw)T ns WAIT hold time (from address)
t
HAWT2 <24> (1.5 + n + tASw + tAHw)T ns
tSSTWT1 <25> n ≥ 1 (1 + tAHw)T − 15 ns WAIT setup time (to ASTB↓)
t
SSTWT2 <26> (1 + n + tAHw)T − 15 ns
tHSTWT1 <27> n ≥ 1 (n + tAHw)T ns WAIT hold time (from ASTB↓)
t
HSTWT2 <28> (1 + n + tAHw)T ns
Address hold time from RD↑ tHRDA2 <29> (1 + i)T − 5 ns
Address hold time from WRm↑ tHWRA2 <30> T − 5 ns
Hold time from RD↑ to CSn tHRDC2 <31> i ≥ 1 T − 5 ns
Hold time from WRm↑ to CSn tHWRC2 <32> T − 5 ns
Remarks 1. tASW: Number of address setup wait clocks
t
AHW: Number of address hold wait clocks
2. T = 1/f
CPU (fCPU: CPU operating clock frequency)
3. n: Number of wait clocks inserted in the bus cycle
The sampling timing changes when a programmable wait is inserted.
4. m = 0, 1
5. i: Number of idle states inserted after a read cycle (0 or 1)
6. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.