Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS
R01UH0042EJ0500 Rev.5.00 Page 1422 of 1513
Aug 12, 2011
33.7.1 CLKOUT output timing
(T
A = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Output cycle tCYK <1> 20.83 ns 31.25 μ s
High-level width tWKH <2> tCYK/2 − 6 ns
Low-level width tWKL <3> tCYK/2 − 6 ns
Rise time tKR <4> 6 ns
Fall time tKF <5> 6 ns
Clock Timing
CLKOUT (output)
<1>
<2> <3>
<4> <5>