Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1393 of 1513
Aug 12, 2011
32.1.5 Operation
The on-chip debug function is made invalid under the conditions shown in the table below.
When this function is not used, keep the DRST pin low until the OCDM.OCDM0 flag is cleared to 0.
OCDM0 Flag
DRST Pin
0 1
L Invalid Invalid
H Invalid Valid
Remark L: Low-level input
H: High-level input
Figure 32-2. Timing When On-Chip Debug Function Is Not Used
Low-level input
After OCDM0 bit is cleared,
high level can be input/output.
Clearing OCDM0 bit
Releasing reset
RESET
OCDM0
P56/INTP05/DRST
32.1.6 Cautions
(1) If a reset signal is input (from the target system or a reset signal from an internal reset source) during RUN
(program execution), the break function may malfunction.
(2) Even if the reset signal is masked by the mask function, the I/O buffer (port pin) may be reset if a reset signal is
input from a pin.
(3) Pin reset during a break is masked and the CPU and peripheral I/O are not reset. If pin reset or internal reset is
generated as soon as the flash memory is rewritten by DMM or read by the RAM monitor function while the user
program is being executed, the CPU and peripheral I/O may not be correctly reset.
(4) In the on-chip debug mode, the DDO pin is forcibly set to the high-level output.