Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1391 of 1513
Aug 12, 2011
32.1.3 Maskable functions
Reset, NMI, INTWDT2, WAIT, and HLDRQ signals can be masked.
The maskable functions with the debugger (ID850QB) and the corresponding V850ES/JG3-H and V850ES/JH3-H
functions are listed below.
Table 32-2. Maskable Functions
Maskable Functions with ID850QB Corresponding V850ES/JG3-H and V850ES/JH3-H Functions
NMI0 NMI pin input
NMI2 Non-maskable interrupt request signal (INTWDT2) generation
STOP
−
HOLD HLDRQ pin input
RESET Reset signal generation by RESET pin input, low-voltage
detector, clock monitor, or watchdog timer (WDT2) overflow
WAIT WAIT pin input
32.1.4 Register
(1) On-chip debug mode register (OCDM) (V850ES/JG3-H only)
The OCDM register is used to select the normal operation mode or on-chip debug mode. This register is a special
register and can be written only in a combination of specific sequences (see 3.4.8 Special registers).
This register is also used to specify whether a pin provided with an on-chip debug function is used as an on-chip
debug pin or as an ordinary port/peripheral function pin. It also is used to disconnect the internal pull-down resistor
of the P56/INTP05/DRST pin.
The OCDM register can be written only while a low level is input to the DRST pin.
This register can be read or written in 8-bit or 1-bit units.