Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY
R01UH0042EJ0500 Rev.5.00 Page 1379 of 1513
Aug 12, 2011
Table 31-9. Relationship Between FLMD0 and FLMD1 Pins and Operation Mode When Reset Is Released
FLMD0 FLMD1 Operation Mode
0 Don’t care Normal operation mode
VDD 0 Flash memory programming mode
VDD VDD Setting prohibited
(3) Serial interface pin
The following shows the pins used by each serial interface.
Table 31-10. Pins Used by Serial Interfaces
Serial Interface Pins Used
UARTC0 TXDC0, RXDC0
CSIF0 SOF0, SIF0, SCKF0
CSIF3 SOF3, SIF3, SCKF3
CSIF0 + HS SOF0, SIF0, SCKF0, P913
CSIF3 + HS SOF3, SIF3, SCKF3, P913
When connecting a dedicated flash programmer to a serial interface pin that is connected to another device on-
board, care should be taken to avoid conflict of signals and malfunction of the other device.
(a) Conflict of signals
When the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to
another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to
the other device or set the other device to the output high-impedance status.
Figure 31-13. Conflict of Signals (Serial Interface Input Pin)
V850ES/JG3-H and
V850ES/JH3-H
Input pin
Conflict of signals
Dedicated flash programmer
connection pins
Other device
Output pin
In the flash memory programming mode, the signal that the dedicated flash
programmer sends out conflicts with signals another device outputs.
Therefore, isolate the signals on the other device side.