Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY
R01UH0042EJ0500 Rev.5.00 Page 1376 of 1513
Aug 12, 2011
31.4.4 Selection of communication mode
In the V850ES/JG3-H and V850ES/JH3-H, the communication mode is selected by inputting pulses (12 pulses max.) to
the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated
flash programmer.
The following shows the relationship between the number of pulses and the communication mode.
Figure 31-9. Selection of Communication Mode
V DD
V DD
RESET (input)
FLMD1 (input)
FLMD0 (input)
RXDC0 (input)
TXDC0 (output)
V
SS
V DD
V SS
V DD
V SS
V DD
V SS
V DD
V SS
V DD
V SS
(Note)
Power on
Oscillation
stabilized
Communication
mode selected
Flash control command communication
(erasure, write, etc.)
Reset
released
Note The number of clocks is as follows depending on the communication mode.
FLMD0 Pulse Communication Mode Remarks
0 UARTC0 Communication rate: 9,600 bps (after reset), LSB first
8 CSIF0 V850ES/Jx3-H performs slave operation, MSB first
9 CSIF3 V850ES/Jx3-H performs slave operation, MSB first
11 CSIF0 + HS V850ES/Jx3-H performs slave operation, MSB first
12 CSIF3 + HS V850ES/Jx3-H performs slave operation, MSB first
Other RFU Setting prohibited
Caution When UARTC0 is selected, the receive clock is calculated based on the reset command sent
from the dedicated flash programmer after receiving the FLMD0 pulse.