Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY
R01UH0042EJ0500 Rev.5.00 Page 1363 of 1513
Aug 12, 2011
Table 31-5. Signal Connections of Dedicated Flash Programmer (PG-FP5)
PG-FP5
V850ES/JG3-H,
V850ES/JH3-H
Processing for Connection
Signal Name I/O Pin Function Pin Name UARTC0
CSIF0,
CSIF3
CSIF0 + HS,
CSIF3 + HS
FLMD0 Output Write enable/disable FLMD0
FLMD1 Output Write enable/disable FLMD1
Note 1 Note 1 Note 1
VDD
−
VDD voltage generation/voltage monitor VDD
GND
−
Ground VSS
CLK Output
Clock output to V850ES/JG3-H and
V850ES/JH3-H
X1, X2 ×
Note 2
×
Note 2
×
Note 2
RESET Output Reset signal RESET
SI/RxD Input Receive signal
SOF0, SOF3/
TXDC0
SO/TxD Output Transmit signal
SIF0, SIF3/
RXDC0
SCK Output Transfer clock SCKF0, SCKF3
×
HS Input
Handshake signal for CSIF0 + HS, CSIF3
+ HS communication
P913
× ×
Notes 1. Wire these pins as shown in Figures 31-6 and 31-7, or connect then to GND via pull-down resistor on board.
2. Clock cannot be supplied via the CLK pin of the flash programmer. Create an oscillator on board and supply
the clock.
Remark
: Must be connected.
×: Does not have to be connected.