Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY
R01UH0042EJ0500 Rev.5.00 Page 1362 of 1513
Aug 12, 2011
(3) CSIF0 + HS, CSIF3 + HS
Serial clock: 5 MHz or less (MSB first)
Figure 31-5. Communication with Dedicated Flash Programmer (CSIF0 + HS, CSIF3 + HS)
V850ES/JG3-H,
V850ES/JH3-H
V
DD
V SS
RESET
SOF0, SOF3
SIF0, SIF3
SCKF0, SCKF3
P913
V DD
FLMD1 FLMD1
Note
FLMD0 FLMD0
GND
RESET
SI
SO
SCK
HS
Dedicated flash
programmer
Note Connect the FLMD1 pin to the flash programmer or connect to GND via a pull-down resistor on the board.
The dedicated flash programmer outputs the transfer clock, and the V850ES/JG3-H and V850ES/JH3-H operate as a
slave.
When the PG-FP5 is used as the dedicated flash programmer, it generates the following signals to the V850ES/JG3-H
and V850ES/JH3-H. For details, refer to the PG-FP5 User’s Manual (U18865E).