Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 27 CLOCK MONITOR
R01UH0042EJ0500 Rev.5.00 Page 1340 of 1513
Aug 12, 2011
(1) Operation when main clock oscillation is stopped (CLME bit = 1)
If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is generated as shown in
Figure 27-2.
Figure 27-2. Reset Period Due to That Oscillation of Main Clock Is Stopped
Four internal oscillation clocks
Main clock
Internal oscillation
clock
Internal reset
signal
CLM.CLME bit
RESF.CLMRF bit
(2) Clock monitor status after RESET input
RESET input clears the CLM.CLME bit to 0 and stops the clock monitor operation. When CLME bit is set to 1 by
software at the end of the oscillation stabilization time of the main clock, monitoring is started.
Figure 27-3. Clock Monitor Status After RESET Input
(CLM.CLME bit = 1 is set after RESET input and at the end of main clock oscillation stabilization time)
CPU operation
Clock monitor status
CLME
RESET
Internal oscillation
clock
Main clock
Reset
Oscillation
stabilization time
Normal
operation
Clock supply
stopped Normal operation
Monitoring Monitoring stopped Monitoring
Set to 1 by software