Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 26 RESET FUNCTIONS
R01UH0042EJ0500 Rev.5.00 Page 1336 of 1513
Aug 12, 2011
26.3.5 Reset function operation flow
Start (reset source occurs)
Main clock
oscillation stabilization
time secured?
No
CCLS.CCLSF bit = 1?
Yes
No
(in normal operation mode)
No
(in emergent operation mode)
Reset source generated?
Yes
No
Yes (in normal
operation mode)
WDT2 overflow?
No
Yes (in emergent operation mode)
Set RESF register
Note 1
Reset occurs →
reset release
Emergent operation
Software processing
Normal operation
CPU operation starts from reset address
(f CPU = f X /8, f R )
Firmware operation
f CPU = f X
f CPU = f R
Note 2
CCLS.CCLSF bit ← 1
WDT2 restart
Internal oscillation and main clock
oscillation start,
WDT2 count up starts
(reset mode)
Notes 1. Bit to be set differs depending on the reset source.
Reset Source WDT2RF Bit CRMRF Bit LVIRF Bit
RESET pin 0 0 0
WDT2 1 Value before reset is retained. Value before reset is retained.
CLM Value before reset is retained. 1 Value before reset is retained.
LVI Value before reset is retained. Value before reset is retained. 1
2. The internal oscillator cannot be stopped.