Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 26 RESET FUNCTIONS
R01UH0042EJ0500 Rev.5.00 Page 1330 of 1513
Aug 12, 2011
26.3 Operation
26.3.1 Reset operation via RESET pin
When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized.
When the level of the RESET pin is changed from low to high, the reset status is released.
Table 26-1. Hardware Status on RESET Pin Input
Item During Reset After Reset
Main clock oscillator (fX) Oscillation stops Oscillation starts
Subclock oscillator (fXT) Oscillation continues
Internal oscillator Oscillation stops Oscillation starts
Peripheral clock (fX to fX/1,024) Operation stops
Operation starts after securing oscillation
stabilization time
Internal system clock (fCLK),
CPU clock (f
CPU)
Operation stops
Operation starts after securing oscillation
stabilization time (initialized to fXX/8)
CPU Initialized
Program execution starts after securing
oscillation stabilization time
Watchdog timer 2 Operation stops (initialized to 0)
Counts up from 0 with internal oscillation
clock as source clock.
Internal RAM
Undefined if power-on reset or CPU access and reset input conflict (data is damaged).
Otherwise value immediately after reset input is retained.
I/O lines (ports/alternate-function
pins)
High impedance
Note
On-chip peripheral I/O registers Initialized to specified status, OCDM register is set (01H).
Other on-chip peripheral functions Operation stops
Operation can be started after securing
oscillation stabilization time
Note When the power is turned on, the following pin may output an undefined level temporarily, even during reset.
• P10/ANO0 pin
• P11/ANO1 pin
• DDO pin (V850ES/JH3-H only)
• P53/SIF2/TIAB00/KR3/TOAB00/RTP03/DDO pin (V850ES/JG3-H only)
Caution The OCDM register is initialized by the RESET pin input. Therefore, note with caution that, if a high
level is input to the P56/INTP05/DRST pin after a reset release before the OCDM.OCDM0 bit is cleared,
the on-chip debug mode is entered. For details, see CHAPTER 4 PORT FUNCTIONS.