Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 26 RESET FUNCTIONS
R01UH0042EJ0500 Rev.5.00 Page 1329 of 1513
Aug 12, 2011
26.2 Registers to Check Reset Source
The V850ES/JG3-H and V850ES/JH3-H have four kinds of reset sources. After a reset has been released, the source
of the reset that occurred can be checked with the reset source flag register (RESF).
(1) Reset source flag register (RESF)
The RESF register is a special register that can be written only by a combination of specific sequences (see 3.4.8
Special registers).
The RESF register indicates the source from which a reset signal is generated.
This register can be read or written in 8-bit or 1-bit units.
RESET pin input sets this register to 00H. The initial value differs if the source of reset is other than the RESET pin
signal.
0
WDT2RF
0
1
Not generated
Generated
RESF 0 0 WDT2RF 0 0 CLMRF LVIRF
After reset: 00H
Note
R/W Address: FFFFF888H
Reset signal from WDT2
LVIRF
0
1
Not generated
Generated
Reset signal from LVI
CLMRF
0
1
Not generated
Generated
Reset signal from CLM
Note The value of the RESF register is set to 00H when a reset is executed via the RESET pin. When a reset
is executed by the watchdog timer 2 (WDT2), low-voltage detector (LVI), or clock monitor (CLM), the
reset flags of this register (WDT2RF bit, CLMRF bit, and LVIRF bit) are set. However, other sources are
retained.
Caution Only "0" can be written to each bit of this register. If writing "0" conflicts with setting the flag
(occurrence of reset), setting the flag takes precedence.