Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 26 RESET FUNCTIONS

R01UH0042EJ0500 Rev.5.00 Page 1328 of 1513

Aug 12, 2011

CHAPTER 26 RESET FUNCTIONS

26.1 Overview

The following reset functions are available.

(1) Four kinds of reset sources

• External reset input via the RESET pin

• Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES)

• System reset via the comparison of the low-voltage detector (LVI) supply voltage and detected voltage

• System reset via the detecting clock monitor (CLM) oscillation stop

After a reset is released, the source of the reset can be confirmed with the reset source flag register (RESF).

(2) Emergency operation mode

If the WDT2 overflows during the main clock oscillation stabilization time inserted after reset, a main clock

oscillation anomaly is judged and the CPU starts operating on the internal oscillation clock.

Caution In emergency operation mode, do not access on-chip peripheral I/O registers other than registers

used for interrupts, port function, WDT2, or timer M, each of which can operate with the internal

oscillation clock. In addition, operation of CSIF0 to CSIF4 and UARTC0 using the externally input

clock is also prohibited in this mode.

Figure 26-1. Block Diagram of Reset Function

CLMRF LVIRFWDT2RF

Reset source flag

Internal bus

WDT2 reset signal

CLM reset signal

RESET

LVI reset signal

Reset signal

Reset signal to

LVIM register

Clear

SetSet

Clear Clear

Set

Caution An LVI circuit internal reset does not reset the LVI circuit.

Remark LVIM: Low-voltage detection register